Display Timing Parameters: Pixel Clock, Blanking, and Sync

Timing parameters are usually learned by accident, when an image appears shifted or a panel refuses to lock. The parameters themselves are simple: a clock, two totals, four intervals and two polarities. What takes time is knowing which one produces which symptom, and how to read a panel timing table without guessing.

Part of the Interfaces, Touch & Signal Integrity guide — 41 articles on RGB, SPI, LVDS, MIPI, eDP and the touch controller.

Why timing matters: blank, shifted and rolling images

A display expects a specific number of pixels per line, a specific number of lines per frame and a defined relationship between the synchronisation signals and the active area. When any of those is wrong, the result ranges from a blank screen to an image that is shifted, wrapped, compressed or vertically rolling. Because several different mistakes produce similar symptoms, the efficient approach is to compare the host’s configuration against the panel’s own timing table rather than to experiment.

The same parameters also determine the data rate, which is why timing errors and bandwidth limits are often confused with one another.

Pixel clock math: total pixels × frame rate

The pixel clock equals the horizontal total multiplied by the vertical total, multiplied by the refresh rate. Increasing resolution raises both totals, and increasing refresh rate raises the multiplier, so either change increases the required clock. That single relationship explains most interface limitations: a link that carries a panel comfortably at 60 Hz may not at 90 Hz, and a host configured for a standard mode may output a clock the panel cannot accept.

The totals include blanking, which is why they are always larger than the active resolution.

The seven numbers that describe a video signal

The pixel clock sets the data rate; the horizontal total is the number of clock cycles per line including blanking; the vertical total is the number of lines per frame; the front and back porches position the sync pulses within the blanking; the sync widths define the pulse lengths; and the sync polarity determines which edge marks the start of the active region. Active resolution is the visible area, and the totals are what a timing entry requires.

Reading a supplier’s table in that order – clock, totals, porches, widths, polarity – builds a valid configuration without gaps.

H and V blanking: front porch, back porch and sync pulse

Blank intervals give the panel’s driver electronics time to switch between lines and frames, and they carry the synchronisation information. Reducing blanking increases the data transmitted per second at the same refresh rate, which is a technique for fitting more resolution into a limited interface at the cost of margin. Where a design is tight, trimming blanking slightly is often preferable to reducing colour depth, provided it stays inside the panel’s specification.

Porch values are also what position the image: shifting them moves the visible area within the frame.

Sync modes: DE-only versus HSYNC + VSYNC

Some panels expect a data-enable signal that marks the active pixels, with horizontal and vertical syncs still present for timing; others accept DE-only operation where the syncs are embedded in the timing. The mode must match what the host generates, because a panel expecting DE-only will behave unpredictably with separate syncs asserted, and vice versa. Where the interface is serial, the equivalent information travels in the packet structure rather than on separate wires.

The mode belongs in the timing table alongside the numbers, not in a footnote.

Checking against the datasheet: register values and ranges

Most panels publish a recommended set of values and a permitted range for each parameter. The recommended set is the safe starting point; the range is what matters when the host cannot produce exactly that configuration. Comparing the host’s register values against the panel’s range, rather than only against the recommended set, shows how much margin exists.

Recording both the recommended and the actual working values in the project file makes later revisions much easier.

Debugging timing problems: symptom-to-cause checklist

Image shifted horizontally: horizontal porch values or sync polarity. Image shifted or wrapped vertically: vertical porches or polarity. Image compressed or stretched: active resolution, or a scaler in the path. Flicker or instability: pixel clock or refresh rate outside the supported range. No image with a valid clock: sync polarity inverted, or a reset released at the wrong time. Working through the list in order is faster than changing values at random.

Where a scaler is present, its own processing delay and output timing are part of the problem, not external to it.

Timing and temperature

Panel driver electronics and interface transceivers change behaviour across the operating range, and a configuration with no margin at room temperature can fail in a cold store or a hot enclosure. Leaving margin in the pixel clock and verifying at both extremes is the practical approach, particularly in wide-temperature products. Where a link trains, the training result at the temperature extremes is worth recording.

Recording the timing parameters that were verified, and the temperature at which they were verified, makes the design record useful later.

Common mistakes and how to avoid them

Five errors account for most timing problems: using active resolution where the total is required; assuming sync polarity instead of reading it; setting the pixel clock at the panel’s maximum with no margin; adding a scaler without accounting for its latency; and copying a timing entry from a similar panel with different totals. Each is avoided by working from the panel’s own table and recording the values used.

Interface specifications that define the underlying signalling are published by MIPI and HDMI.org, and practical design guidance appears in vendor material such as TI’s LVDS application note, with further signal-chain documentation from Analog Devices and STMicroelectronics.

Verifying a timing configuration

Four checks confirm the setup: display a full-screen test pattern and confirm no shift, wrap or border; measure the actual frame rate and compare it with the calculated value; confirm the pixel clock at the panel connector with a scope or frequency counter; and repeat at the temperature extremes with the content used in service. These take under an hour and produce the record a later revision will need.

Related reading: display controllers, GRAM and refresh, when to use the RGB parallel interface and interface checks before design freeze.