Why Timing Matters: Blank, Shifted, and Rolling Images

A TFT panel is written one line at a time, in a fixed order. The host (or a controller board) supplies three kinds of signals to keep that order:

• Pixel clock (PCLK): one pulse per pixel transferred.
• Horizontal sync (HSYNC) and blanking: mark the end of one line and the gap before the next.
• Vertical sync (VSYNC) and blanking: mark the end of one frame and the gap before the next frame.

When these signals disagree with what the panel expects, the panel cannot map pixels to the correct positions. The image shifts sideways, rolls vertically, tears, or collapses into garbage. In other words, timing parameters are not a formatting detail; they are the contract between your timing source and the panel. The values come from the panel datasheet, and your controller must generate a signal inside the ranges the datasheet allows.

Pixel Clock Math: Total Pixels × Frame Rate

The pixel clock is the rate at which every pixel slot—active pixels plus blanking—is clocked in one second:

Pixel clock ≈ (horizontal total) × (vertical total) × (frame rate)

where horizontal total = active width + horizontal blanking and vertical total = active height + vertical blanking. Blanking is part of the clock budget, not wasted overhead you can ignore.

Worked example (assumed blanking, not a panel specification). Suppose you want to drive an 800×480 panel at 60 Hz. You choose a horizontal total of 1,056 pixels and a vertical total of 525 lines—values that sit in the middle of typical small-panel timing tables:

Pixel clock ≈ 1,056 × 525 × 60 ≈ 33.3 MHz

If the datasheet quotes a minimum pixel clock of, say, 25 MHz and a maximum of 40 MHz, this value fits. If your frame rate or blanking changes, the clock changes with it.

To build the totals yourself from a datasheet, add the porches and sync width to the active area:

Htotal = Hactive + H front porch + HSYNC width + H back porch
Vtotal = Vactive + V front porch + VSYNC width + V back porch

Some datasheets state the totals directly; others state only active pixels plus the porch and sync ranges. When only ranges are given, start with the typical values, compute the clock, and keep the result inside the datasheet’s pixel clock limits. Choosing a total at the low end of the allowed range lowers the pixel clock and power; choosing a total near the high end leaves more time for the panel’s internal logic. Neither is “correct” by itself—what matters is that the value you program matches the panel’s allowed timing window.

These rows use assumed blanking totals to demonstrate the calculation only. Always use the active area and blanking values from your target panel’s datasheet, then confirm the result falls inside the panel’s pixel clock range.

If the difference between a direct-drive interface and a buffered controller matters for your design, the interface decision is covered separately in our guide to when to use RGB parallel, and controller-side GRAM and refresh behavior in display controllers explained.

H and V Blanking: Front Porch, Back Porch, and Sync Pulse

Blanking is the time when no active pixel data is sent. Each line contains a sync pulse, a back porch, the active pixels, and a front porch:

• Front porch: the gap after the last active pixel of a line (or frame) before the sync pulse.
• Sync pulse: the HSYNC or VSYNC assertion that tells the panel a new line or frame is starting.
• Back porch: the gap after the sync pulse before the first active pixel.

Horizontal blanking gives the panel’s timing logic time to move to the next line; vertical blanking gives it time to start the next frame. Panels state these as ranges (for example, a minimum front porch and a typical back porch), and the host is expected to produce values inside those ranges. There is no single “correct” blanking set that works for every panel—two panels with the same active resolution can require different totals.

Because blanking values live inside the timing table, checking them is part of reading the datasheet rather than a separate design skill. When an image is shifted but stable, the usual suspects are horizontal or vertical totals that disagree with the panel’s expectations.

A concrete way to visualize one horizontal period: the panel draws the sync pulse, waits through the back porch, writes the active pixels left to right, then waits through the front porch before the next sync pulse. If you change the back porch, every line shifts relative to the sync pulse; if you change the front porch, the panel simply waits longer before starting the next line. That is why “shifted image” maps so directly to “porch or total mismatch” in the debug table later in this guide.

Sync Modes: DE-Only vs HSYNC + VSYNC

Panels accept timing in one of two common modes:

• DE-only mode: a Data Enable signal is high only while active pixels are valid. The panel derives line and frame timing from the DE pattern, and HSYNC/VSYNC are not used. This mode is common on interfaces that embed sync information in the serial stream, such as LVDS or MIPI-DSI.
• HSYNC + VSYNC mode: the host supplies separate horizontal and vertical sync pulses. This is typical on parallel RGB interfaces, where the panel expects discrete sync lines plus DE.

Which mode your project needs depends on the interface and the controller, not on the panel alone. If you are choosing between LVDS and MIPI-DSI, or deciding whether an RGB parallel interface fits your host, those are separate decisions covered in our LVDS vs MIPI-DSI guide.

You can usually identify the mode from the datasheet pin list: if the panel only exposes DE, it expects DE-only timing; if it exposes HSYNC and VSYNC pins, it can use discrete sync. The panel’s register guide then tells you which mode the controller is configured for. When both are possible, DE-only reduces pin count and is the common choice on serial interfaces, while discrete sync gives you explicit control over line and frame timing on a parallel bus.

Checking Against the Datasheet: Register Values and Ranges

Before you write a single register, build a small comparison table from the datasheet’s timing section:

1. Pixel clock: find min/typ/max PCLK; compute your required clock and confirm it sits inside the range.
2. Horizontal parameters: note HSYNC pulse width, front porch, back porch, and horizontal total range.
3. Vertical parameters: note VSYNC pulse width, front porch, back porch, and vertical total range.
4. Signal polarity: confirm whether sync and DE are active-high or active-low.
5. Sync mode: confirm whether the panel accepts DE-only, HSYNC+VSYNC, or both.

Then compare every register value you configure against that table. A value that is inside “typical” on one panel can be outside the allowed range on a similar-looking panel, so treat the datasheet as authoritative for that specific model. If the controller’s clock source cannot reach the required range, the fix is a different clock configuration or a controller with a suitable range—not forcing the panel to accept out-of-range timing.

Three mismatches appear over and over in practice:

• Polarity reversed: the datasheet says HSYNC is active-low, but the host drives active-high. The image shifts or rolls even though every number looks correct.
• Total instead of porch: the host is configured with a correct-looking porch but a total that ignores the sync pulse width, pushing the real total outside the allowed range.
• DE polarity wrong in DE-only mode: the panel inverts the meaning of DE and treats active pixels as blanking, producing a blank or inverted image.

These are configuration faults, not panel faults. Checking polarity alongside the numeric values saves a debugging cycle that otherwise looks like a hardware problem.

Debugging Timing Problems: Symptom-to-Cause Checklist

Use the symptom to narrow the cause before changing registers one at a time:

Change one parameter at a time and re-test: timing faults interact, and moving two values at once makes it hard to tell which one fixed the image. If the image is stable but the panel’s refresh behavior still looks wrong, the mechanism lives inside the controller or the panel’s GRAM, which is covered in our controller GRAM and refresh guide.

When the symptom persists after the table checks, measure rather than guess: confirm the pixel clock frequency on a scope or logic analyzer, then confirm the horizontal and vertical totals by counting pulses between sync edges. If the measured totals match your configuration and the image is still wrong, compare polarity and DE behavior next. Only after those pass should you suspect the panel itself—swap in a known-good panel of the same model to isolate the fault, then check the cable and connector, because intermittent shifted lines are often a contact or shielding problem rather than a timing register problem.

Frequently Asked Questions

Formula and standard-signal descriptions in this article are general engineering facts; all worked numbers use assumed blanking values and are labeled as examples. Product-specific limits must come from the panel datasheet.