eDP Link Training and AUX Channel Troubleshooting

An embedded display panel that fails eDP link training after a cold start leaves a log entry and a black screen. The message is true and almost useless. Link training has stages, and a failure in clock recovery points to a different physical problem from a failure in channel equalization. Reading the two separately, per lane and per attempt, turns a binary failure into a diagnosis. This guide sets out the stage record, the lane-status interpretation and the corner tests that expose a marginal link before it reaches the field.

Which eDP link training failure stage is reported?

Separate clock recovery failure from equalization failure.

Clock recovery establishes lane timing before equalization adjusts voltage and pre-emphasis; a log reporting only a final failure hides which stage exhausted its retries.

An eDP main link is trained in two conceptual stages. Clock recovery brings the receiver’s timing into lock with the transmitted symbol stream. Channel equalization then adjusts the transmitter’s drive and pre-emphasis so that the receiver can recover symbols reliably across the channel. The link also needs symbol lock and interlane alignment before video can be sent. A failure can occur at any of these points, and the remedy differs.

A clock recovery failure suggests that the receiver cannot establish timing: the lane may be too attenuated, the reference clock may be wrong, or the lane may not be carrying a valid stream. An equalization failure suggests that timing is present but the signal quality is insufficient: the channel may be lossy, the AC-coupling may be wrong, or the transmitter’s settings may be unsuitable for the cable. Treating both as link training failed removes the information needed to choose the next test. The panel drawing, read alongside the LCD datasheet parameter guide, defines which rates and lane counts the panel actually supports.

The first logging change is therefore to record the stage at which each attempt stopped, not only the final result. The second is to record it per lane, because a four-lane link can fail on one lane while the others train cleanly.

How should lane status be interpreted across retries?

Lane status must be read per lane and per attempt.

A success after several failed attempts differs from a clean first attempt; record each lane’s status at every stage, because a marginal lane can pass once and fail cold.

Link training is iterative. The transmitter may adjust pre-emphasis and voltage swing, the receiver may request a different setting, and the link may retry at the same rate or fall back. A log that records only the final success loses the number of attempts, the settings used and the lane that was marginal. That information is often the difference between a cable that is slightly too lossy and a connector that is intermittently open.

Record the status of each lane at each stage: whether clock recovery completed, whether equalization completed, whether symbol lock was achieved and whether interlane alignment completed. Then record the retry count and the settings at each attempt. If one lane consistently needs more retries than the others, the problem is local to that lane’s path. If all lanes degrade together, the cause is more likely to be a shared reference clock, a common power rail or a link-rate setting.

A single successful training result is not proof of margin. It is proof that the link worked once under those conditions. The log should make that distinction explicit, so a later failure is compared with a baseline rather than treated as an anomaly.

When does a lower link rate provide diagnostic value?

A lower rate can isolate timing from signal integrity.

Falling back to a lower rate reduces bandwidth demand, so a link that trains there but not at full rate points to margin, equalization or routing.

A lower link rate is a controlled experiment, not a permanent solution. If the link trains at a lower rate and fails at the intended rate, the receiver and transmitter can establish timing, and the failure is likely to be channel margin, equalization or a rate-dependent setting. If the link fails at every rate, the problem is more likely to be a missing clock, a wiring error, a power issue or a lane that is not connected at all.

The experiment should change one variable at a time. Keep the lane count, cable and temperature constant and change only the rate. Record the result at each rate. Then repeat with a different lane count, because a link that works with two lanes but not four may have a problem on one pair rather than a general bandwidth shortage.

The result should be recorded as a diagnostic finding, not as an approved operating mode. Shipping at a lower rate reduces the available bandwidth and may affect resolution, refresh or EMC. If a lower rate is proposed as the product configuration, it needs its own validation and a documented reason.

Which connector and routing checks follow a lane-specific error?

A single failing lane points to that lane’s path.

Check connector mating, pair routing, AC-coupling capacitors and via stubs for the affected lane, then compare with a known-good cable before changing PHY settings.

A lane-specific failure is a physical clue. Inspect the connector for a bent or recessed contact, contamination or incomplete mating. Check the pair routing for a sharp bend, a long stub, a reference-plane split or a via that is much longer than its neighbours. Verify the AC-coupling capacitors on the affected lane and confirm their value and orientation. On the panel side, inspect the flex and the connector for damage.

Swap the cable for a known-good one before changing the host’s PHY settings. A cable swap is cheap and reversible; a register change may mask the problem and make the next build worse. If the failure follows the cable, the cable is the finding. If it stays with the host, the board or the connector is the finding. If it stays with the panel, the panel or its flex is the finding.

The TI guidance on LVDS impedance and termination describes the matching discipline for differential channels; the same principle applies to an eDP main link, where the channel and its termination are designed together.

How do spread-spectrum settings affect compatibility testing?

Spread-spectrum settings must match across the link.

A host and panel or bridge that disagree on spread-spectrum modulation can fail training intermittently, so record the setting in the test matrix.

Spread-spectrum clocking reduces peak emissions by modulating the clock frequency. It is useful for EMC, but it adds a variable to link training: the receiver must tolerate the modulation, and the transmitter and receiver must be configured consistently. A host that enables spread spectrum while the bridge or panel expects a fixed clock can show intermittent training failures that depend on temperature, cable length or the particular unit.

Treat spread spectrum as a test condition. Record whether it is enabled at the host, at the bridge and at the panel, and test the combinations that the product will ship with. Do not assume that a setting which works on one board will work on another, because the modulation profile and the reference clock can differ.

If a failure disappears when spread spectrum is disabled, that is a finding, not a fix. The product may still need spread spectrum for EMC, so the underlying margin problem has to be addressed rather than hidden by changing the clock. Record the EMC requirement and the training result together so the trade-off is visible.

When should firmware fall back rather than loop?

Bound the retries and define a fallback state.

Repeated retraining hides a marginal link and delays the user; firmware should stop after a defined count, fall back to a documented mode and log the sequence.

A retry loop can keep a product in a black-screen state while the link repeatedly attempts to train. The user sees a failure with no diagnosis, and the log fills with identical attempts. A bounded policy is better: attempt training a defined number of times, then fall back to a documented mode or report a fault. The count and the fallback should be design decisions, not defaults inherited from a driver.

The fallback has to be a state the product can actually use. Falling back to a lower rate or lane count may preserve an image, but only if the resolution and refresh remain acceptable and the panel supports the mode. Falling back to a lower resolution may be better than a black screen for a service display, but unacceptable for a measurement display. Define the priority before the failure occurs.

Log the sequence, not just the outcome. The number of attempts, the stage that failed, the settings used and the fallback taken are all part of the record. The Linux DRM KMS documentation describes the display pipeline and mode responsibilities; the driver’s link-training policy sits behind that interface and should be visible in the log.

Which corner conditions reveal marginal training?

Test cold, hot, low voltage and cable extremes.

Training margin changes with temperature, supply voltage, cable length and connector wear, so the corner matrix should reproduce them and record where each attempt fails.

A link that trains at room temperature with a short cable may fail at the cold limit, at the low end of the supply range or with the production cable length. The corner matrix should include the minimum and maximum operating temperature, the supply voltage limits, the longest and shortest cable in the build, and a connector that has been mated repeatedly. If the product is exposed to vibration, include a vibration or flex condition that moves the cable.

At each corner, record the training result and the stage at which it failed. A failure that appears only at cold suggests a timing or reference-clock margin issue; a failure that appears only at low supply suggests a drive or power issue; a failure that appears only with a particular cable suggests channel loss. The pattern is more useful than a single pass or fail.

Repeat the corner test after any change to the cable, connector, bridge firmware or panel revision. The Linux device power management documentation is relevant because resume paths often retrain the link, and a corner failure may appear first after suspend rather than at boot.

What must the training log retain for escalation?

Keep the versioned stage, lane and retry record.

An escalation needs host and panel revisions, bridge firmware, cable identifier, lane status per stage, retry counts, temperature and supply voltage.

A supplier cannot investigate a link-training failure from a single error message. The log should identify the host and its driver version, the bridge or panel revision, the cable part and length, the lane count and rate, the spread-spectrum setting, the temperature and the supply voltage. It should also record the stage status per lane for each attempt and the fallback that was taken.

Keep the log versioned with the firmware that produced it. A register dump without the firmware revision cannot be interpreted, and a training log without the panel revision cannot be matched to a build. If the failure is intermittent, keep the failed attempts as well as the successful one; the pattern of retries is often the only evidence of a marginal link.

The table below shows the minimum record for a training escalation. It is a template, not a set of limits; the limits come from the host, bridge and panel datasheets and from the product requirements.

eDP link-training escalation record

Host or bridge setting	Panel requirement	Cable or pin condition	Diagnostic evidence	Compatibility decision
Four-lane, full rate	Panel supports lane count and rate	Length, impedance, AC coupling	Per-lane stage status and retries	Pass or fail at intended mode
Two-lane fallback	Mode still within panel capability	Same cable and connector	Stage status after fallback	Diagnostic only unless approved
Lower link rate	Timing and bandwidth remain valid	Same cable and connector	Training result at each rate	Diagnostic isolation
Spread spectrum on	Panel or bridge tolerance	Reference clock and routing	Training result with setting recorded	Test condition, not a fix
Cold or low-voltage corner	Operating range	Production cable and connector	Stage failed and temperature	Margin assessment

The bridge datasheet defines what the device supports. The SN65DSI86 documents eDP auxiliary-channel, link-training and lane configuration behaviour for that device, while the SN65DSI83 documents a different bridge function and is not a substitute for eDP training evidence. Use the datasheet for the device in the design, and keep the revision with the log.