SPI TFT Partial Update: Reduce Transfer Time Without Breaking Update Boundaries

SPI TFT partial update is a transaction-cost problem, not only a payload problem. A small SPI TFT can take longer to update a status icon than to redraw the whole screen, because each partial update pays for address commands, chip-select transitions and a fixed setup time. The saving must therefore be measured in time, not only in bytes. This guide shows how to size the address window, count the bytes actually sent, merge regions sensibly, and keep DMA and chip select aligned so the last bytes are not lost.

When can an SPI TFT partial update reduce the actual payload?

Partial refresh pays off when the changed area is small.

Payload falls with area only if the controller accepts a window and the transfer does not have to send a full-width stride for every line.

A partial update sends only the pixels inside a rectangle. If the rectangle is much smaller than the screen, the payload can fall dramatically. But the saving depends on the controller: some devices accept a column and page window and write only the pixels inside it, while others advance the address by the full display width for every line, which forces a full-width transfer even for a narrow region.

The saving also depends on the transaction overhead. Each region needs address commands, a chip-select transition and a setup time before the first pixel. A small region with a large fixed overhead may take as long as a larger region sent in one transaction. The comparison must use measured time, not just bytes.

A full-frame update also has a fixed overhead, so the comparison should use the same bus clock and controller configuration. Record the region size, the bytes sent and the measured duration. A design that assumes a proportional saving without measuring will often be disappointed.

Which address-window commands define a region?

Column and page address commands define the window.

The controller needs start and end column and page values before the memory-write command; the window must match the pixel format and orientation.

Most SPI TFT controllers define a column address window and a page address window before a memory-write command. The host sets the start and end column, then the start and end page, then issues the write command and streams pixels. The controller places the pixels inside that window and advances through it according to its address counter.

The window must match the pixel format and the panel orientation. A window defined in landscape coordinates will be wrong if the panel is rotated, and a window defined in the wrong colour depth will write the wrong number of bytes. Some controllers require the window to be aligned to a boundary, especially for 16-bit or 18-bit formats.

Some controllers auto-increment through the window and wrap at the end; others stop and require a new command, which changes the transaction count. Record the exact command sequence, the coordinate system and the alignment rule. The controller manual for the actual device is the authority; a sequence from another controller may use different commands or a different address order.

How do stride and pixel format affect transferred bytes?

Stride can force a full-width transfer per line.

If the controller writes a full line for each row, the saved payload shrinks; check whether the window advances by region width or display width.

The payload is the number of pixels in the region times the bytes per pixel, but only if the controller advances by the region width. If it advances by the full display stride, each line of the region carries the full width, and the saving is much smaller. The controller’s address-counter behaviour determines which case applies.

Pixel format adds another factor. An RGB565 pixel uses two bytes, while an RGB666 pixel may use three bytes and an RGB888 pixel four. The byte count in the window is the pixel count times the bytes per pixel, plus any padding required by the controller. A partial update that assumes 16-bit pixels when the panel is configured for 18-bit will send the wrong number of bytes and leave the region incomplete.

If the panel is rotated, the window coordinates must be transformed, and the transformed region may not be a simple rectangle in memory. Record the stride behaviour, the pixel format and the resulting byte count. The LVGL 9.2 display porting guide documents the draw-buffer and flush side, but the controller’s addressing rule comes from its own manual.

When do many small regions cost more than one large region?

Command overhead can make many small regions slower.

Each region needs address commands, chip-select transitions and setup, so several small updates can cost more than one bounding box.

A screen with several changed icons may produce several small dirty rectangles. Sending each one separately multiplies the address commands and the chip-select transitions. A single bounding box that contains all of them sends more pixels but fewer transactions. The faster option depends on the fixed cost per transaction relative to the pixel rate.

Measure both strategies on the actual bus. A rough model is useful for choosing candidates, but the SPI clock, the command overhead and the controller’s write timing determine the result. If the fixed cost is high, merge aggressively; if the pixel rate is low, a smaller region may still be faster.

Record the region count, the total bytes and the measured time for each strategy. A policy based on pixel count alone can choose the slower option.

How should DMA completion and chip-select timing be aligned?

Chip select must remain active until the last byte.

DMA completion may occur before the bus is idle; if chip select rises early, the controller can drop final bytes or latch an incomplete write.

SPI transfers are framed by chip select. The controller expects the command and the pixel data to arrive while chip select is active, and it may interpret a rising edge as the end of the transaction. If the driver raises chip select when the DMA transfer is queued rather than completed, the last bytes can be lost or the controller can latch an incomplete write.

Wait for the DMA completion event and, where the peripheral provides it, the bus-idle or transfer-complete flag before deasserting chip select. Check the SPI peripheral’s FIFO status as well; a completion interrupt may fire while the last byte is still in the shift register.

A logic-analyzer capture should include chip select, clock, MOSI and the panel’s busy or TE signal if it has one. The ST AN4839 cache note is relevant when the region is built in cached memory. Record the event that gates chip select and the measured last-byte timing. A logic-analyzer capture of chip select, clock and data is the clearest evidence.

What does the controller allow during an active scan?

Writes during scan may be allowed, with tearing as the cost.

Some controllers accept writes at any time, some require a blanking or TE window, and some ignore writes during scan; the manual defines which applies.

A TFT controller with GRAM scans continuously. A memory write that lands while the scan is reading the same region can produce a tear. Some controllers accept the write and show the tear; some buffer it; some require the host to wait for a blanking interval or a TE signal. The manual defines the behaviour.

If the controller has a TE output, the host can align the write to a safe window. If it does not, the host can still reduce tearing by writing quickly or by updating a region that the scan has already passed. The strategy depends on the controller and the panel.

A controller that buffers the write may still tear if the buffer is smaller than the region. Record the synchronization method and the observed result. A partial update that ignores the scan may look correct on a static image and tear during animation.

Which patterns test stale edges and missed regions?

Moving boxes and text expose stale edges and missed regions.

A small rectangle moving across a static background leaves a trail if the old region is not cleared, and text reveals a missed column.

A small rectangle moving across a static background is the classic stale-edge test. If the old position is not cleared, a trail remains. If the new position is written one column short, the rectangle has a missing edge. A line of text moving horizontally shows the same errors at a finer scale.

Use a background with a known pattern, such as a checkerboard or a grid, so a missed region is visible. A flat background hides a stale pixel or a one-column gap. Test at the panel’s orientation and at any rotation the product supports.

Record the pattern, the region coordinates and the observed result. A test that only draws a static logo cannot reveal a partial-update boundary error.

What transfer-budget table supports the chosen refresh policy?

The table records region, bytes, transactions and time.

For each policy, record region size, pixel format, bytes transferred, transactions and measured time, then compare with the full-frame cost.

The table should let another engineer choose between a full-frame update, a single bounding box and several small regions. For each policy, record the region or regions, the pixel format, the bytes transferred, the number of transactions, the measured time and the resulting frame rate. Add the bus clock and the controller configuration.

Include the worst case, not only the average. A screen with many small updates may be fast on average and slow when several icons change at once. The policy should be chosen for the worst case the product allows.

The table below is a template. It is not a set of limits; the values come from the controller manual and the measured bus timing.

SPI partial-update transfer budget

Workload or state	Pixel or buffer format	Measured traffic or energy	Constraint	Evidence source
Full-frame update	RGB565	All pixels in one transaction	Frame time budget	Logic-analyzer capture
Single icon	RGB565	Window pixels plus commands	Address command overhead	Measured transaction
Multiple icons	RGB565	Separate windows or one bounding box	Transaction count	Comparison capture
Scrolling region	RGB565	Full-width band	Stride behaviour	Controller manual
Rotation change	RGB565	Redraw of affected area	Coordinate transform	Visual and trace check

The ST AN4861 LTDC application note is an example of controller-side buffer and timing documentation for a different display path; the SPI controller’s own manual remains the authority for its address window. The LVGL display module documentation illustrates the same buffer and arbitration thinking for a different display path. The small bar TFT SPI and I2C guide covers the interface choice for compact displays, and the LVGL rotation documentation covers the buffer consequences of rotation.