STM32 LTDC Framebuffer Bandwidth: Budget SDRAM Access Under Concurrent DMA

STM32 LTDC framebuffer bandwidth is often blamed on the CPU when the memory system is the limit. An STM32 display that runs a static screen perfectly and breaks into horizontal bands during a blended animation is usually short of memory bandwidth, not short of CPU. The LTDC reads the framebuffer continuously, DMA2D may be writing another layer, and the CPU is using the same SDRAM. This guide builds a workload-aware bandwidth worksheet, shows how pixel format and refresh change the demand, and defines the FIFO-underflow evidence that proves the design is marginal.

Which STM32 LTDC framebuffer bandwidth terms need calculation?

Start with resolution, format, layers and refresh.

Basic read traffic is width times height times bytes per pixel times refresh, multiplied by active layers and increased by blending or DMA2D reads.

The LTDC reads each active layer from memory for every frame. The basic read traffic is the layer width times its height times the bytes per pixel times the refresh rate. If two layers are enabled, both are read. If a layer is blended, the LTDC may also read the destination or an additional source, depending on the configuration.

That calculation gives the minimum read demand. It does not include the CPU, DMA2D, Ethernet, USB or other masters that share the same memory. The usable bandwidth is the SDRAM’s derated capability after refresh, bank conflicts, bus turnaround and arbitration. The design is viable when the sum of all masters, plus a margin, fits inside the usable bandwidth.

A layer that is not visible still costs nothing, so the layer count should be the number actually enabled in the hardware, not the number allocated in the application. Write the worksheet with each term visible. A single number that says “the framebuffer needs X MB/s” hides the assumptions and cannot be checked when the resolution or the layer count changes.

How do pixel format and refresh change memory traffic?

Higher colour depth and refresh both raise read traffic.

ARGB8888 reads twice the bytes of RGB565 at the same resolution, and doubling refresh doubles per-second demand, so the changes compound.

Pixel format sets the bytes per pixel. RGB565 uses two bytes, RGB888 uses three, and ARGB8888 uses four. A layer that is stored as ARGB8888 but displayed without alpha still costs four bytes per pixel unless the storage format is changed. Converting the framebuffer to a smaller format can halve or quarter the read traffic, at the cost of colour depth or alpha.

Refresh rate multiplies the per-frame traffic. Doubling the refresh doubles the per-second demand, and it also shortens the time available for other masters between frames. A design that is comfortable at 30 Hz may be marginal at 60 Hz even though the image content is identical.

If the framebuffer is rotated or the layer is offset, the read pattern becomes less sequential, which lowers the SDRAM efficiency even when the byte count is unchanged. Record the format, the layer count and the refresh together. The ST AN4861 LTDC application note documents framebuffer access and pixel formats for the listed STM32 families.

What additional traffic comes from blending and DMA2D?

Blending and DMA2D add reads and writes beyond scan-out.

A blended layer needs source read, destination read and destination write, and DMA2D operations compete with LTDC for the same memory bus.

Blending is memory-intensive. A simple copy reads a source and writes a destination. A blend may read the source, read the destination and write the result, which is three accesses for the same pixels. If the operation is repeated for several layers, the traffic multiplies. DMA2D can perform these operations efficiently, but it does not make the memory accesses disappear.

The LTDC and DMA2D share the memory bus with the CPU and other DMA masters. When DMA2D is copying a large image, the LTDC’s FIFO may not be refilled quickly enough, and the display shows a band or a frozen line. The contention is the problem, not the average bandwidth alone.

A DMA2D operation that runs once per frame is different from one that runs on every touch event; the worksheet should state the rate as well as the size. Record the DMA2D operations in the worksheet, including the source and destination formats and the number of pixels. A design that budgets only for scan-out will underestimate the load during a transition or an animation.

Which SDRAM timing and bus-arbitration limits apply?

SDRAM efficiency and arbitration decide usable bandwidth.

Theoretical bus rate is reduced by refresh, bank conflicts, turnaround and arbitration; LTDC shares the bus with CPU, DMA and other masters.

The SDRAM datasheet gives a peak rate for ideal bursts. Real access includes refresh cycles, row activation, bank conflicts and bus turnaround between read and write. Those effects reduce the effective bandwidth, sometimes substantially. The LTDC also competes with the CPU, DMA2D, Ethernet and other masters, and the arbiter decides which one wins.

Use a measured or derated efficiency in the worksheet, not the peak number. The derating depends on the access pattern: sequential reads are more efficient than random accesses, and read/write mixing costs more than pure reads. The memory controller’s configuration and the SDRAM clock also matter.

A memory controller configured for low latency may sacrifice bandwidth, and the opposite is also true, so the configuration belongs next to the estimate. Record the SDRAM part, clock, bus width, controller configuration and the assumed efficiency. If the design is close to the limit, the efficiency assumption is the first thing to verify with a measurement.

How should FIFO underflow be detected and logged?

Underflow shows as FIFO error flags and visible corruption.

The LTDC FIFO error interrupt, a lost-frame counter or visible tearing can indicate underflow; log timestamp, active layers and concurrent DMA.

The LTDC has a FIFO that buffers pixel data before it is sent to the display. If the memory system cannot refill it in time, the FIFO underflows and the output is corrupted. The controller may raise an error interrupt, set a status bit or simply produce a visible band. Enable the error interrupt where available and log the timestamp, the active layers, the refresh rate and the concurrent DMA workload.

A lost-frame counter or a frame-start interrupt can also reveal underflow if the frame timing slips. Pair the log with a visual capture, because a corrupted band can have other causes.

If the controller has no error interrupt, a periodic frame counter or a visible band pattern can serve as a proxy, provided the test is repeatable. Record the log in a way that survives a reset if the failure is intermittent. A counter that is cleared at boot loses the evidence that the previous session produced.

What stress workload reproduces a marginal design?

Blended full-screen motion plus DMA is the stress case.

Combine multiple layers, alpha blending, full-screen movement and concurrent DMA, then run long enough to expose a rare underflow.

A static screen is not a bandwidth test. The stress case should include the maximum number of layers, the largest pixel format, alpha blending, full-screen movement and a concurrent DMA2D or CPU memory load. Run it at the maximum refresh and at the temperature and supply corners the product specifies.

Include the production logging and communication traffic. A design that passes with logging disabled can fail when the product writes a log or receives a network packet. The stress workload should resemble the real product, not a benchmark.

Run the same workload at the lowest and highest ambient temperature, because SDRAM timing and the controller’s margin change with temperature. Run long enough to catch a rare event. A short animation may never hit the worst-case arbitration pattern. Record the duration and the result.

When does lowering refresh provide useful evidence?

A refresh sweep shows whether bandwidth is the limit.

If underflow disappears at lower refresh and returns at the intended rate, the design is bandwidth-limited; if it persists, suspect arbitration or configuration.

Lowering the refresh reduces the per-second read demand and lengthens the time between frames. If the underflow disappears at a lower refresh and returns at the intended rate, the memory system is close to its limit. That is evidence of a bandwidth problem, not a panel problem.

If the underflow persists at a much lower refresh, the cause is more likely to be a configuration error, a cache-coherency issue, an SDRAM timing problem or a DMA master that is monopolizing the bus. The sweep rules out the simple bandwidth explanation and points to a different test.

Record the refresh values and the underflow result at each, and state whether the lower-refresh result is a diagnostic or a candidate product mode. A diagnostic result is not a release decision. A single pass at a lower refresh does not qualify the product; it identifies the limit.

What assumptions belong in the bandwidth worksheet?

State format, layers, frame rate and efficiency.

Record resolution, pixel format, layer count, refresh, blending, DMA2D traffic, SDRAM efficiency and margin, so another engineer can reproduce it.

The worksheet should show each term: resolution, bytes per pixel, layer count, refresh, blending reads and writes, DMA2D traffic, other masters and the assumed SDRAM efficiency. Add the margin and the measured result. If a term is unknown, mark it as an open assumption rather than leaving it out.

Include the memory map and the cache configuration. A buffer placed in a slower memory region or a cacheable region with poor coherency can change the result. The ST AN4839 cache application note describes the cache behaviour that affects those accesses, and the LVGL 9.2 display porting guide documents the draw-buffer side of the same path.

The table below is a template for the worksheet. It is not a set of limits; the values come from the STM32, memory and panel documents.

LTDC bandwidth and underflow record

Workload or state	Pixel or buffer format	Measured traffic or energy	Constraint	Evidence source
Static single layer	RGB565	Scan-out read traffic	Refresh and bus efficiency	Worksheet and counter
Two blended layers	ARGB8888 and RGB565	Source and destination reads	LTDC FIFO depth	Underflow log
DMA2D full-screen copy	Matching source and destination	Read plus write traffic	Bus arbitration	DMA counter and trace
CPU memory load	Application buffers	Concurrent read/write traffic	Arbiter priority	Stress run
Refresh sweep	Same layers and format	Traffic at each refresh	Underflow result	Test log

The ST AN4861 LTDC application note covers the interaction between the controller and the memory masters. The eDP bandwidth guide covers the link side of a high-resolution display, and the LVGL rotation documentation covers the buffer consequences of rotation; this page owns the memory side.