Timing parameters are usually learned by accident, when an image appears shifted or a panel refuses to lock. The parameters themselves are simple: a clock, two totals, four intervals and two polarities. What takes time is knowing which one produces which symptom, and how to read a panel timing table without guessing.

The seven numbers that describe a video signal

Everything else is derived from these.

The pixel clock sets how fast pixels are transmitted. The horizontal total is the number of clock cycles per line including blanking, and the vertical total is the number of lines per frame. Within those, the front porch and back porch define the positions of the sync pulses relative to the active area, and the horizontal and vertical sync widths define the pulse lengths. Sync polarity determines which edge marks the start of the active region. Together these seven values describe the whole signal.

Active resolution is the visible area; the totals are always larger because blanking time is required between lines and frames. Confusing the two is one of the most common sources of a wrongly constructed timing entry.

Reading a panel timing table

Suppliers present the same information in different orders.

Typical timing table fields and their symbols

Field	Common symbol	What it controls
Pixel clock	DCLK	Data rate and refresh rate
Horizontal active and total	H active / H total	Image width and line period
Vertical active and total	V active / V total	Image height and frame period
Front and back porch	HFP, HBP, VFP, VBP	Position of sync within blanking
Sync widths	HSW, VSW	Pulse length
Sync polarity	HSYNC / VSYNC polarity	Which edge starts the active period

Reading the table in this order – clock, totals, porches, widths, polarity – builds a valid timing entry without gaps. Where the supplier gives a recommended set of values as well as a range, the recommended set is the safer starting point.

Symptom to parameter: a mapping

Diagnosis is faster when the mapping is known.

• Image shifted horizontally: horizontal porch values or sync polarity.
• Image shifted vertically or wrapped: vertical porch values or polarity.
• Image compressed or stretched: active resolution, or a scaler in the path.
• Flicker or instability: pixel clock or refresh rate outside the supported range.
• No image with a valid clock: sync polarity inverted, or reset released incorrectly.

Having this list available during bring-up turns an afternoon of guessing into a sequence of defined checks.

How refresh rate and pixel clock relate

The arithmetic is short and worth memorising.

The refresh rate equals the pixel clock divided by the product of the horizontal total and the vertical total. That single relationship explains most interface limitations: increasing the refresh rate requires a higher pixel clock, and increasing resolution raises the totals, so both increase the data rate. Where an interface is near its limit, the designer chooses which of the three to reduce, and doing so deliberately avoids the surprise of an unexpected frame rate.

For bar formats the totals are unusual but the arithmetic is the same, which is why a 1920×360 panel can run comfortably on an interface that would struggle with a full-HD panel at the same refresh rate.

Blanking, bandwidth and interface overhead

Blanking exists for a reason, and it costs bandwidth.

Blank intervals give the panel’s driver electronics time to switch between lines and frames, and they also carry the synchronisation information. Reducing blanking increases the data transmitted per second for the same refresh rate, which is a technique used to fit more resolution into a limited interface – at the cost of margin. Where a design is tight, reducing blanking slightly is often preferable to reducing colour depth, provided it stays inside the panel’s specification.

Serial interfaces carry their own overhead in addition to blanking, which is why the same pixel clock may be feasible on a parallel link and marginal on a serial one.

Timing and temperature

Margin is consumed by temperature.

Panel driver electronics and interface transceivers change behaviour across the operating range, and a configuration with no margin at room temperature can fail in a cold store or a hot enclosure. The practical approach is to leave margin in the pixel clock and to verify the configuration at both extremes, particularly in wide-temperature products where the range is broad.

Recording the timing parameters that were verified, and the temperature at which they were verified, makes the design record useful later.

Common mistakes and how to avoid them

Five errors account for most timing problems.

1. Using active resolution where the total is required.
2. Assuming sync polarity instead of reading it from the table.
3. Setting the pixel clock at the panel’s maximum with no margin.
4. Adding a scaler without accounting for its latency and processing delay.
5. Copying a timing entry from a similar panel with different totals.

Each of these is avoided by working from the panel’s own table and recording the values used. CDTech’s notes on timing parameters and on display controllers, GRAM and refresh cover the supporting detail, and interface specifications are published by MIPI and HDMI.org.

Verifying a timing configuration

Four checks confirm the setup.

• Display a full-screen test pattern and confirm no shift, wrap or border.
• Measure the actual frame rate and compare it with the calculated value.
• Confirm the pixel clock at the panel connector with a scope or frequency counter.
• Repeat at the temperature extremes with the content used in service.

These four checks take under an hour and produce the record a later design revision will need. Vendor documentation such as TI’s LVDS application note is useful when interpreting measurements.