Display Pixel Clock Jitter: Decide What to Measure Before Changing the Panel

Display pixel clock jitter is often blamed for an unstable edge, but the term covers several different faults. An image with occasional pixel errors or an unstable edge is often blamed on the panel before anyone defines what “clock jitter” means for this interface. Cycle-to-cycle jitter, long-term drift and a closed data eye are different faults with different fixes. This guide sets the measurement point, the probe limits and the report fields, then separates a genuine clock problem from a data-setup problem that only looks like one.

Where should display pixel clock jitter be measured?

Measure at the panel clock input, not the controller.

The panel sees the clock after board, connector and cable, so probe at its input pin with a low-capacitance setup and record the point.

The clock at the controller output is not the clock the panel receives. The board trace, the connector, the cable and the panel’s input capacitance all shape the edge and add delay. A jitter measurement taken at the controller can look clean while the panel sees a distorted or delayed clock. The measurement point should be the panel’s clock input pin, or as close to it as the layout allows.

For a differential clock, measure the pair differentially rather than probing one side against a distant ground. For a single-ended clock, keep the ground return short and referenced to the panel’s ground. Record the exact point, including the connector pin or test pad, so the result can be repeated.

If the panel has no accessible clock pin, measure at the connector and state that the result excludes the panel’s internal load. That limitation belongs in the report; it is not a reason to move the measurement back to the controller without saying so.

Which instrument bandwidth and probing limits matter?

Probe and scope bandwidth must exceed the clock rate.

Too little bandwidth rounds the edge and hides high-frequency jitter, while a long ground lead adds inductance and ringing that looks like jitter.

The measurement system must have enough bandwidth to capture the edge and the jitter that matters. A probe with a bandwidth close to the clock frequency will round the transition and under-report high-frequency content. The scope’s sample rate and record length determine the time resolution and the observation window, and both should be stated.

The probe’s loading matters as much as its bandwidth. A high-capacitance probe can slow the edge and change the circuit’s behaviour. A long ground lead adds inductance and picks up interference. Use a low-capacitance probe with a short ground return, and verify the setup on a known-good clock before measuring a suspect one.

A differential probe also rejects common-mode noise that a single-ended probe would include in the jitter reading. Record the probe model, attenuation, bandwidth, ground arrangement, scope bandwidth, sample rate and record length; the TI LVDS owner’s manual covers the differential signalling behind the measurement. A jitter number without those fields cannot be compared with another measurement or reproduced by a supplier.

How do cycle-to-cycle and long-term jitter differ?

Cycle-to-cycle is short-term; period jitter is longer.

Cycle-to-cycle compares adjacent periods and exposes high-frequency noise, while long-term error captures drift, spread spectrum and low-frequency modulation.

Cycle-to-cycle jitter measures the difference between one clock period and the next. It is sensitive to high-frequency noise, supply ripple and crosstalk, and it is the quantity most closely related to whether a receiver can sample the data reliably. A clock with large cycle-to-cycle jitter can close the data eye even when its average frequency is correct.

Long-term jitter, often expressed as time-interval error or period jitter over many cycles, captures slower variation: drift with temperature, spread-spectrum modulation and low-frequency supply movement. It matters for frame timing and for interfaces that rely on a stable average rate, but it does not describe the same risk as cycle-to-cycle jitter.

Report which definition was used. A number labelled jitter without a definition is ambiguous, and two measurements can disagree because they measured different things. The display timing parameters guide covers the pixel clock and blanking context around this measurement.

What can clock-source substitution establish?

A substituted clock separates source from channel.

Driving the panel from a known-good clock removes the host PLL; if the image improves, the source or its supply is implicated, not the cable.

Substitution is a controlled experiment. Replace the host clock with a clean signal generator or a known-good board, keeping the panel, cable and pattern unchanged. If the image becomes stable and the measured jitter falls, the original clock source or its supply is the problem. If the image remains unstable, the channel or the panel input is the more likely cause.

The substitute must meet the panel’s electrical requirements: the correct frequency, swing, common mode and edge rate. A signal generator that is cleaner but out of specification can produce a different failure and confuse the result. Record the substitute’s settings and verify its output at the panel input.

Substitution does not prove that the original source is defective; it shows that the fault moves with the source. That is enough to choose the next test, whether a supply measurement, a PLL configuration review or a board swap.

How should supply ripple be correlated with image errors?

Correlate clock edges with rail ripple on one capture.

Capture clock and supply together; a jitter burst that follows a ripple peak points to PLL or driver sensitivity, not the panel input.

A clock source and its output drivers are sensitive to supply noise. When the rail ripples, the edge timing moves, and the receiver may sample the wrong bit. The effect can be intermittent because it depends on the phase between the ripple and the data pattern.

Capture the clock and the relevant supply rail on the same time base, with a trigger that shows the image error or the error interrupt. If the jitter burst follows a ripple peak, the source or its supply is implicated. If the jitter is present without ripple, the clock source itself or the channel is the better suspect.

Repeat the capture with the backlight at a different brightness, because the driver’s switching can couple into the clock rail. Record the rail, the measurement bandwidth and the probe arrangement. A supply measurement with a long ground lead can show ripple that is not present at the device, or hide ripple that is.

When is an apparent clock fault actually a data-setup problem?

A closed data eye can look like clock jitter.

If data arrives too late or early relative to the clock, the receiver samples the wrong bit; check setup and hold before blaming the clock.

The receiver samples data on a clock edge. If the data arrives too late or too early relative to that edge, the sampled value is wrong, and the resulting pixel error can look like a clock problem. The clock may be perfectly clean while the data eye is closed by a long trace, a bad termination, a level shifter or a cable with excessive skew.

Measure the data and the clock together at the panel input and check the setup and hold margin. If the data transition is too close to the sampling edge, the fault is a timing or channel problem, not clock jitter. The fix may be a shorter trace, a different output delay, a termination change or a different clock edge.

The TI guidance on LVDS impedance and termination covers the channel side of that margin. This distinction prevents replacing a panel or a clock source for a data-path problem. The DS90C385A datasheet is an example of a transmitter that specifies setup and hold relationships for its parallel input; those limits apply to that device and its channel.

Which corner tests establish usable margin?

Vary temperature, supply and pattern at the panel input.

Measure at cold and hot limits, at low and high supply, and with patterns that change data and refresh load, then compare the margin.

Jitter and setup margin change with temperature, supply voltage and data pattern. A clock that is clean at room temperature can fail at the cold limit, where the driver is weaker, or at the hot limit, where leakage and delay change. A pattern that keeps the data bus quiet can hide crosstalk that appears with a full-screen animation.

Run the measurement at the product’s specified corners, with the production cable and connector. Include at least one pattern with high transition density and one with low density, because the two exercise different coupling paths. Record the margin at each corner, not just pass or fail.

A corner that passes with no recorded margin gives no warning when the next board revision changes the layout. If the margin is small at one corner, the design is marginal even if it passes. The report should state the worst corner and the measured margin, so a later change can be judged against it.

What should a clock-quality report state explicitly?

Report point, instrument, jitter type and conditions.

A usable report names measurement point, probe and scope bandwidth, sample rate, jitter definition, supply and temperature, and the image result.

The report should be reproducible by someone who was not present. State the measurement point, the probe model and bandwidth, the ground arrangement, the scope bandwidth, the sample rate and the record length. Name the jitter definition and the analysis window. Record the supply voltage, temperature, pattern and refresh rate. Add the observed image result and whether the fault correlated with a supply or clock event.

State what was not measured. If the panel’s internal load was excluded, say so. If the clock was measured single-ended rather than differentially, say so. Those limitations are part of the evidence.

The table below is a template for the report. It is not a set of limits; the limits come from the panel timing specification and the host datasheet.

Supply railPLL and driver supply rangeDecoupling and traceRipple correlated with jitterApproved if noise is bounded

Pixel-clock jitter evidence record

Host or bridge setting	Panel requirement	Cable or pin condition	Diagnostic evidence	Compatibility decision
Clock output at controller	Panel input frequency and swing	Trace and series element	Reference measurement only	Not sufficient alone
Clock at panel input	Panel sampling requirements	Connector and cable	Differential probe and jitter record	Approved if margin remains
Data at panel input	Setup and hold	Pair skew and termination	Data and clock captured together	Approved if eye is open
Spread-spectrum setting	Panel tolerance	Same clock path	Measurement with setting recorded	Approve in shipping state

The DRM KMS documentation covers the pipeline and mode context; the electrical measurement remains a board-level task. A bridge such as the SN65DSI83 has its own output timing and must be included when it is the clock source.