Dual-Channel LVDS Odd/Even Pixels: Verify Port Order and Image Splits

Dual channel LVDS odd even pixels are easy to describe and hard to debug. The panel lights, the image is stable, and every second column is wrong or the two halves are exchanged. A firmware change may appear to fix it, then break a different resolution. This guide separates the link order from the split architecture, shows which patterns expose a reversal, and defines the pin-by-pin record that keeps a dual-link build reproducible.

How are dual channel LVDS odd even pixels assigned?

Each link carries alternate pixels of the same frame.

Dual-channel LVDS splits the stream across two links, usually odd and even pixels, so each link runs at half the pixel rate and the panel rebuilds the order.

A dual-channel LVDS interface uses two serial links to carry one frame. In the common odd/even architecture, the first link carries every other pixel and the second carries the remaining pixels. Each link runs at half the pixel rate of a single-link interface of the same resolution, which is why dual-channel LVDS is used for larger or higher-resolution panels.

The panel reconstructs the frame by interleaving the two streams. If the links are exchanged, the interleave order reverses: the panel places even pixels where odd pixels belong. The result can be a one-pixel shift, a striped image or a colour error, depending on the content and on how the panel’s internal logic handles the swap.

The assignment is defined by the panel drawing and the transmitter configuration, not by the connector alone. The TI LVDS owner’s manual describes the differential signalling and mapping conventions behind these links; the panel drawing remains the authority for its own order. Record which physical pair group belongs to link 0 and link 1, which pixels each carries and which clock accompanies it. The DS90C385A datasheet is an example of a transmitter that documents its parallel-to-LVDS mapping and clock relationship for its own device.

Which source and sink naming conventions conflict?

Naming conventions conflict between source and sink.

One document may call the first link odd and the second even, while another uses A/B or 0/1; names do not establish which pair carries which pixel.

Datasheets use several naming schemes for the same two links: channel A and B, link 0 and 1, primary and secondary, odd and even, or first and second. The names are not standardised across vendors, and a document may use one term for the physical port and another for the pixel order. A source that calls its output odd may be connected to a panel that calls the same stream even.

The only reliable definition is the pair assignment at the connector and the pixel order the panel expects. Build a table that maps each physical pair to a link name, a pixel order and a clock. Then compare the source table, the cable drawing and the panel table. If the names differ, translate them into the physical assignment rather than assuming that odd means the same thing at both ends.

The LVDS versus MIPI comparison covers the interface choice at a higher level; this page owns the dual-link naming and order record.

What patterns identify reversed link order?

One-pixel vertical stripes expose a reversed link order.

Alternating single-pixel columns invert or shift when the links are exchanged, while a symmetric checkerboard can look correct and hide the error.

A pattern of alternating black and white single-pixel columns is the most direct test. Each link carries one of the two column types. If the links are exchanged, the pattern inverts or shifts by one pixel, and the error is visible across the whole screen. A moving vertical bar produces a similar result and is easier to see on a small panel.

A symmetric checkerboard can hide the swap because the pattern looks the same after the exchange. A flat field hides it completely. A gradient may show a subtle banding or a doubled step, but the cause is harder to identify. Use at least one pattern with unequal neighbouring pixels and one with an asymmetric feature.

Record the pattern, the link order and the observed result. If the image changes when the links are swapped at the connector, the order is the finding. If it does not, the panel may use a left/right split rather than odd/even, or the swap may be inside the cable rather than at the connector.

How do odd/even and left/right split architectures differ?

Odd/even interleaves pixels; left/right splits the screen.

Odd/even assigns alternate pixels to each link, while left/right assigns half the screen to each; the same swap produces a different symptom.

In an odd/even architecture, the two links carry interleaved pixels from the same horizontal line. A swap reverses the interleave and produces a one-pixel shift or a stripe pattern. In a left/right architecture, each link carries a contiguous half of the screen. A swap exchanges the halves, producing a vertical seam at the centre or a mirrored layout.

The two architectures can use the same connector and the same number of pairs, so the connector does not tell you which one applies. The panel drawing does. If the symptom is a vertical seam with the left and right halves exchanged, the panel is likely using a left/right split. If the symptom is an interleaved stripe, it is likely odd/even.

Record the architecture in the interface specification. A firmware or bridge setting that assumes one architecture will not fix a panel that uses the other, and a test pattern designed for one may not expose the other.

Which clock relationships must be verified?

Both link clocks and their skew must be verified.

Each link has its own clock relationship to its data, and the two must be aligned closely enough for the panel to rebuild the frame without a seam.

Each LVDS link carries a clock pair alongside its data pairs. The transmitter must place the clock edge within the data eye, and the receiver must sample at the correct point. In a dual-link system, the two links may share a clock source or use separate clocks, depending on the transmitter and panel. The panel drawing defines which arrangement it expects.

Measure each link’s clock at the panel connector and compare the two. Check the skew between the links, the duty cycle and the amplitude. A large skew can shift one link relative to the other and produce a seam even when the logical mapping is correct. A weak or distorted clock can cause intermittent sampling errors that look like a mapping fault.

Record the clock arrangement: shared or separate, the source, the measured skew and the probe setup. The TI LVDS impedance and termination guidance covers the channel and termination side of the same interface.

How can cable swaps create misleading symptoms?

A cable swap can mimic a firmware or panel fault.

Exchanging the links at one connector can reverse the order or swap halves, producing symptoms that look like timing or panel defects.

A cable that swaps the two link groups at one end is electrically valid and mechanically possible, especially when the connector has two similar row groups. The result depends on the architecture: an odd/even panel shows an interleaved error, and a left/right panel shows exchanged halves. In both cases, the image may be stable enough to look like a firmware configuration problem.

The swap can also occur inside the cable assembly, not at the connector. A harness built for a different panel may cross the pairs in the middle. Continuity testing at the connector will not reveal it unless the test is referenced to the panel’s pin assignment rather than to the cable’s own labels.

Before changing firmware, verify the physical mapping with a continuity test and a known-good cable. If the symptom follows the cable, the cable is the finding. If it stays with the board, the transmitter or connector is the finding.

What should be measured before changing firmware?

Measure both links before changing any register.

Scope each link’s clock and data, confirm which pixels it carries and compare the two before editing firmware; a wrong assumption can hide the cause.

Capture each link’s clock and at least one data pair at the panel connector, with a pattern that makes the assignment visible. Confirm which link carries the odd pixels and which carries the even pixels by comparing the data with the known pattern. Measure the clock skew between the links and the timing of the first active pixel.

A bridge such as the SN65DSI83 has its own output mapping and timing limits, so its configuration belongs in the same comparison. Then read the transmitter or bridge registers and compare them with the panel drawing. If the register says odd/even and the panel expects left/right, the configuration is wrong. If the register and the drawing agree but the capture shows the opposite, the cable or the connector is wrong. The measurement tells you which layer to change.

Changing firmware first is tempting because it is fast, but it can mask a physical swap and produce a build that works only with one cable. The measurement is the cheaper path.

What belongs in a dual-link acceptance record?

The record names every link, clock and pixel order.

The record should list link assignment, pixel order, clock relationship, cable pinout, test patterns and the result for each approved build.

The acceptance record should state which physical pairs belong to each link, which pixels each link carries, whether the architecture is odd/even or left/right, and how the clocks are related. It should include the cable pinout, the connector orientation and the panel revision. The test patterns and their results belong with it, so a later build can be compared with the approved baseline.

Add the measured skew and the probe conditions. A record that says the link works without stating how it was measured cannot be reproduced when a new cable or panel is introduced.

The table below is a template for that record. It is not a set of limits; the values come from the transmitter, cable and panel documents.

Dual-link LVDS acceptance record

Host or bridge setting	Panel requirement	Cable or pin condition	Diagnostic evidence	Compatibility decision
Link 0 assigned odd pixels	Panel expects odd on link 0	Pair group and clock match drawing	Stripe pattern and data capture	Approved
Link 1 assigned even pixels	Panel expects even on link 1	Pair group and clock match drawing	Stripe pattern and data capture	Approved
Link order reversed	Panel order unchanged	Connector or harness crossed	Pattern inverts or shifts by one pixel	Reject or rewire
Left/right architecture	Panel splits screen in half	Each link reaches its half	Half-screen swap or centre seam	Approve only for that panel
Clock shared	Panel expects shared clock	Clock pair routed to both links	Skew and duty measurement	Approved if within panel limit

The DRM KMS documentation covers the display pipeline context in which the dual-link mode is configured; the physical link order remains a board and cable property. A panel supplier can confirm the expected order and clock arrangement from the drawing, but the verification belongs to the product’s bring-up record.